Analog-to-digital converters using multistage bandpass delta sigma modulators with arbitrary center frequency

ABSTRACT

An architecture for oversampled delta-sigma (Δ--Σ) analog-to-digital (A/D) conversion of high-frequency, narrow-band signals includes multistage Δ--Σ modulators that incorporate band-reject noise shaping centered at an arbitrary center frequency F bp . These modulators cascaded with a bandpass digital filter centered at the arbitrary center frequency F bp  perform A/D conversion for high-frequency, narrow-band signals having the same arbitrary frequency. The bandpass modulators are implemented by use of resonators which provide a substantially large gain at the arbitrary frequency.

BACKGROUND OF THE INVENTION

This invention relates in general to analog-to-digital (A/D) convertersand, more particularly, to a new architecture for oversampleddelta-sigma (Δ--Σ) A/D conversion of high frequency, narrow band signalsusing cascaded low order stages with an arbitrary center frequency toobtain high overall order of noise shaping.

Single-loop bandpass delta-sigma (Δ--Σ) modulation is described by R.Schreier and M. Snelgrove in "Bandpass Sigma Delta Modulation,"Electronics Letters, Vol. 25, Nov. 9, 1989, pp. 1560-1561. Z. X. Zhang,G. C. Temes and Z. Czamul in "Bandpass ΔΣ A/D Converter Using Two-PathMultibit Structure", Electronics Letters, Vol. 27, Oct. 24, 1991, pp.2008-2009, citing Schreier et al., supra, describe a modification of thebasic structure using N-path switched capacitor circuits. Subsequently,R. Schreier, G. C. Temes, A. G. Yesilyurt, Z. X. Zhang, Z. Czarnul, andA. Hairapetian in "Multibit Bandpass Delta-Sigma Modulators Using N-PathStructures", IEEE International Symposium on Circuits and Systems, May1992, pp. 593-596, describe simulation results of two switched-capacitorcircuits for use in a multi-bit bandpass sigma-delta modulator.

Typically, cascaded low-order delta-sigma stages have been used toimplement higher order delta-sigma modulators for A/D conversion oflow-pass signals. See, for example, D. B. Ribner, "A Comparison ofModulator Networks for High-Order Oversampled Sigma-DeltaAnalog-to-Digital Converters," IEEE Trans. Circuits and Systems, Vol.CAS-38, No. 2, pp. 145-159, Feb. 1991. Those cascades comprisecombinations of first and second-order individual stages and therebyavoid the stability problem prone to single-loop modulators ofthird-order and higher. See also D. B. Ribner U.S. Pat. Nos. 5,084,702,5,103,229, and 5,148,166, all assigned to the present assignee, forfurther background on plural-order sigma-delta analog-to-digitalconverters. U.S. Pat. Nos. 5,084,702, 5,103,229 and 5,148,166 are herebyincorporated by reference.

U.S. Pat. No. 5,283,578, issued Feb. 1, 1994, by D. B. Ribner and D. H.K. Hoe, assigned to the present assignee and herein incorporated byreference, provides an architecture for multistage delta-sigma (Δ--Σ)bandpass modulators that provide band-reject noise shaping at one fourththe sampling frequency F_(s). Although the foregoing multistagearchitecture, advantageously overcomes many of the problems of previoussingle stage high order architectures, such as stability, componentspread and design complexity, the center frequency of the bandpassmodulators therein is limited to one fourth of the sampling frequencyF_(s).

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a newarchitecture for oversampled delta-sigma (Δ--Σ) analog-to-digital (A/D)conversion of high-frequency, narrow-band signals which is not limitedto a single center frequency.

Briefly, in accordance with a preferred embodiment of the invention, anarchitecture for multistage delta-sigma (Δ--Σ) bandpass modulatorshaving an arbitrary bandpass frequency F_(bp) situated below at leastone half of the sampling frequency Fs is provided. The bandpassmodulators of the present invention may be implemented with a resonatorhaving z domain transfer function ##EQU1## which when cascaded with abandpass digital filter centered at the arbitrary center frequencyF_(bp) can perform A/D conversion for high-frequency, narrow-bandsignals centered at the same arbitrary frequency. In the aboveequations, z is the discrete time frequency variable. As used herein θis an arbitrary phase angle defined by

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be betterunderstood from the following detailed description of the invention withreference to the accompanying drawings where like numerals representlike elements and in which:

FIGS. 1 and 2 are block diagrams of respective architectures forband-pass multistage Δ--Σ A/D converters which operator a single centerfrequency;

FIG. 3 is a functional block diagram of the discrete time resonatoremployed in the present invention;

FIG. 4 is a block diagram of one stage of a band-pass Δ--Σ A/D converterin accordance with the present invention;

FIG. 5A is a block diagram in a modulation stage of a resonatoremploying integrators according to one aspect of the invention, and FIG.5B is a schematic diagram of a switched-capacitor implementation of thecircuitry of FIG. 5A;

FIG. 6A is a block diagram in modulation stage of a resonator employingintegrators according to another aspect of the invention, and FIG. 6B isa schematic diagram of a switched-capacitor implementation of thecircuitry of FIG. 6A; and

FIGS. 7 and 8 are block diagrams of a multistage Δ--Σ A-D converterimplemented in accordance with the teachings of the present inventionand based on the architectures shown in FIGS. 1 and 2, respectively.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 and 2 illustrate examples of band-pass modulators having acenter frequency limited to one fourth of the sampling frequency F_(s).More particularly, FIG. 1 illustrates a Multiple Second-Order Cascade(MSOC) modulator that is capable of cosinusoidal noise shaping of order2N so as to suppress quantization noise about the aforementioned centerfrequency. The MSOC modulator generates a sampled-data digital responsey(nT) to a sampled-data input voltage x(nT), which response is suppliedto a decimation filter (not shown) that provides the ultimateanalog-to-digital (A/D) conversion result. The MSOC modulator isillustrated as having N stages, although such modulator typically isimplemented with no more than three stages since mismatches and low gaincause leakage of lower order quantization noise to the output andthereby limit performance.

Stage 1, the first Δ--Σ stage 10, includes a two-input adder 11 to whichthe analog sampled-data input voltage x(nT) is supplied as an inputsignal to a first input of adder 11. Adder 11 is also supplied with afirst analog feedback signal as the input signal to its second input.The resulting combined output signal from adder 11 constitutes a firsterror signal, which is scaled in a scaling element 12 by a scalingcoefficient k₁ and then processed by a first resonator 13 to generate aresonator output voltage I₁. Specifically, as disclosed in U.S. Pat. No.5,283,578, the resonator transfer function ##EQU3## provides an infinitegain at a frequency F_(s) /4 which allows the Δ--Σ modulator stage tohave a center frequency corresponding to F_(s) /4. Integrator outputvoltage I₁ is digitized in an A/D converter 14 to generate, for thefirst Δ--Σ modulator stage 10, a digital output signal V₁ thatcorresponds to the sampled-data input signal x(nT). A digital-to-analog(D/A) converter 15 converts the A/D converter 14 output voltage V₁ intothe aforementioned first analog feedback signal which is supplied toadder 11 as the input signal at its second input for completing thefirst feedback loop. The first analog feedback signal voltage from D/Aconverter 15 is also supplied to a first input of another two-inputadder 16. Adder 16 receives at its second input the resonator outputsignal I₁ scaled by a scaling coefficient h₁ in a scaling element 17.Adder 16 generates a combined signal -Q₁ that corresponds to thenegative of the quantization noise of the first Δ--Σ modulator stage 10and, after scaling by a scaling coefficient j₁ of a scaling element 18,is used as an input signal for the second Δ--Σ modulator stage which, inthe illustration, is ith Δ--Σ modulator stage 20.

The ith Δ--Σ modulator stage 20 includes a two-input adder 21 receivingat its first input, the scaled negative quantization noise of apreceding (i-1)th Δ--Σ modulator stage which, in the embodimentillustrated, is the first Δ--Σ modulator stage 10. Adder 21 is suppliedwith the analog feedback signal of the ith Δ--Σ modulator stage 20 asthe input signal to its second input. The resulting combined outputsignal from adder 21 is the ith error signal, which is scaled in ascaling element 22 by a scaling coefficient k_(i) and then processed bya resonator 23 to generate ith resonator output signal I_(i). Theresonator output signal I_(i) is digitized in an A/D converter 24 togenerate a digital output signal V_(i) that corresponds to the negativeof the scaled quantization noise of the preceding Δ--Σ modulator stagewhich, in the embodiment illustrated, is the first Δ--Σ modulator stage10. A D/A converter 25 converts the A/D converter 24 output signal V_(i)to an analog signal constituting the ith analog feedback signal suppliedto adder 21 at its second input, completing the ith feedback loop. Theith analog feedback signal is also supplied to another two-input adder26 at its first input. Adder 26 receives at its second input the ithintegrator output signal I_(i) scaled by a scaling element 27 withscaling coefficient h_(i). Adder 26 generates a combined signal -Q_(i)that corresponds to the negative of the quantization noise of the ithΔ--Σ modulator stage 20 and, after scaling by a scaling element 28 withscaling coefficient j_(i), is used as an input signal voltage for the(i+1)th Δ--Σ modulator stage or, in the embodiment illustrated, Nth Δ--Σ modulator stage 30.

The Nth Δ--Σ modulator stage 30 includes a two-input adder 31 receivingat its first input, the negative of the scaled quantization noise of thepreceding (N-1)th modulator stage or, in the embodiment illustrated, theith Δ--Σ modulator stage 20. Adder 31 is supplied with the analogfeedback signal of the Nth Δ--Σ modulator stage 30 at its second input.The resulting combined output signal from adder 31 is the Nth errorsignal, which is scaled in a scaling element 32 by a scaling coefficientk_(N) and then processed by a resonator 33 to generate Nth resonatoroutput signal I_(N). The resonator output signal I_(N) is digitized inan A/D converter 34 to generate a digital output signal V_(N) thatcorresponds to the negative of the scaled quantization noise of thepreceding Δ--Σ modulator or, in the embodiment illustrated, the ith Δ--Σmodulator 20. A D/A converter 35 converts the A/D converter 34 outputsignal V_(N) to an analog signal as the Nth analog feedback signal whichis supplied to adder 31 at its second input completing the Nth feedbackloop.

The output signals of the ith and Nth Δ--Σ modulator stages 20 and 30are scaled by multipliers 41 and 42, respectively, with scalingcoefficients g_(i-1) and g_(N-1), respectively. The V₁ output signal ofthe first Δ--Σ modulator stage 10 is delayed by a delay element 43 tocompensate for the delay in the V_(N) output signal of the Nth Δ--Σmodulator stage 30. The V_(i) output signal of the ith Δ--Σ modulatorstage 20 is likewise delayed and additionally digitally filtered in adelay and cosine filter 44. Finally, the V_(N) output signal of the NthΔ--Σ modulator 30 is filtered in a cosine filter element 45. The outputsignals of elements 43, 44 and 45 are combined by a digital adder 46 togenerate the digital output signal y(nT).

The type of Δ--Σ MSOC modulator shown in FIG. 1 uses the differencebetween A/D and D/A signals of each stage as the input signal to thefollowing stage and is termed a quantization cascaded modulator,designated MSOC1. The scaling coefficients g_(i), h_(i), j_(i), andk_(i), where i=1 . . . N for this and the following prior art modulatorsof FIG. 2, are discussed in the Ribner paper, supra. In FIG. 1, however,##EQU4## for stage i, and ##EQU5## for stage N, while h_(i) =1/k_(i) forstage i, (where i=1 . . . N), where k₁ through k_(N) are arbitrarycoefficients, typically equal to or less than unity. For example, such kcoefficients are typically equal to unity if respective multi-bit A/Dand D/A converters are used. However, it is generally preferred to userespective one-bit A/D and D/A converters so as to obtain superiorlinearity in any given modulation stage, and in this case such kcoefficients are usually less than unity without affecting the transferfunction of any individual modulation stage. Similarly, j₁ throughj_(N-1) are also arbitrary and typically equal to unity. Thesecoefficients are used for signal scaling.

FIG. 2 shows a Multiple Second Order Cascade modulator, designatedMSOC2, which differs from the MSOC1 modulator shown in FIG. 1 in thatthe resonator output signal of a stage is taken directly as the inputsignal to the following stage; this is termed a resonator cascadedmodulator. Again, practical implementations have been limited to threestages or less due to matching and finite gain constraints. In FIG. 2,##EQU6## for stage i ##EQU7## for stage N, and k₁ through k_(N) arearbitrary coefficients and typically equal to or less than unity, whilej₁ through j_(N-1) are also arbitrary and typically equal to unity, asdiscussed in the context of FIG. 1.

The multistage modulators shown in FIGS. 1 and 2 use digital networks tocombine the individual output signals from the multiple stages into asingle output signal that is supplied to the input of a subsequentdigital decimation filter (not shown). In each case, the resultingoutput signal from any of these modulators is of the form

    Y(z)=z.sup.-2N X(z)+g.sub.N-1 (1+z.sup.-2).sup.N Q.sub.N (z) (2)

for MSOC1 and MSOC2, where Q_(N) is the quantization noise of stage N.

Bandpass modulators of the present invention may be implemented byutilizing a resonator 200, as shown in FIG. 3, instead of the resonatorof the type shown in FIGS. 1 and 2. Specifically, instead of employingthe z domain transfer function ##EQU8## the following resonator transferfunction ##EQU9## is employed. The transfer function of Eq. 4 differsfrom the transfer function of Eq. 3 in that the pair of complexconjugate poles at z=e.sup.±jπ /2 is advantageously transformed to apair of complex conjugate poles at z=e.sup.±jθ. Thus the originalresonator with infinite DC gain at a single frequency of F_(s) /4 isreplaced by a resonator with infinite gain at an arbitrary frequencyF_(bp), preferably situated at least one half below the samplingfrequency F_(s) in order to satisfy the Nyquist sampling raterequirement. As used herein θ=2πF_(bp) /F_(s).

The above transformation may be illustrated by the modulation stagerepresentation of FIG. 4. Specifically, a Δ--Σ modulator stage 100 whichhas an arbitrary center frequency F_(bp) can be implemented when theinput signal, e.g., x(nT), is supplied to an input delay unit 202 togenerate a delayed analog input signal. A two-input adder 204 whoseoutput is coupled to resonator 200 receives the delayed analog inputsignal at its first input and a suitable feedback analog signal at itssecond input. Resonator 200 as illustrated in FIG. 4, includes a scalingcoefficient k₁, usually less than unity, without affecting the overallcharacteristics of resonator 200 illustrated in FIG. 3 with scalingequal to unity. The feedback signal supplied to adder 204 is generatedin feedback generator 206, as will be explained shortly hereafter, inresponse to the output signal of D/A converter 15 which is coupled toA/D converter 14 and which in turn receives the output signal ofresonator 200.

One modulation stage 100' implementation using a resonator constructedwith basic integrating units in accordance with one aspect of theinvention is illustrated in FIG. 5A. In particular, resonator 200'includes an analog subtracter 210 which receives a minuend input analogsignal and a feedback subtrahend signal for producing a differenceoutput signal. An integrator 212 receives the difference output signalto generate a first integrated output signal in response thereto. Adelayed integrator 214 delays and integrates the first integrated outputsignal to generate a second integrated output signal in responsethereto. The second integrated output signal is the output signal ofresonator 200'. For the embodiments shown in FIGS. 4 and 5A the kscaling coefficients can be conveniently selected such that h₁ =1/k₁(FIG. 4) or h₁ =1/k_(la) k_(lb) (FIG. 5). In each case, as suggested inthe context of FIGS. 1 and 2, such k coefficients cooperate to providean overall scaling coefficient which can be equal to or less than unitydepending on the particular modulation stage design. In contrast, thefollowing coefficients are specifically chosen such that a₁ =-k₁ 2Cosθ;a₂ =k₁ ; and b₁ =2(1-Cos θ) so as to provide suitable scaling regardlessof the value of the arbitrary bandpass frequency at which the Δ--93modulator stage is operated. Further, it will be appreciated from FIGS.4 and 5A that feedback generator 206 comprises, by way of example andnot of limitation,both a scaling unit and a delay unit which cooperateto generate the analog feedback signal supplied to the second input ofadder 204.

A practical implementation for the modulation stage of FIG. 5A employsswitched capacitor (SC) integrators, as shown in FIG. 5B. In particular,the analog sampled-data input voltage, e.g., x(nT), is supplied to onepole of a single-pole, double throw (SPDT) sampling switch 110. Thisswitch in practice is implemented with semiconductor switching devicesbut, for simplicity of illustration, is shown as a mechanical switch.The analog sampled-data input voltage x(nT) is supplied by switch 110 toa capacitor 111 having a capacitance value g₁ C₁ to charge capacitor 111to the input voltage level during a first switching period when theother side of capacitor 111 is connected by SPDT switch 112 to ground.Also during the first switching period, switch 112 connects a capacitor113 to ground. Switch 112, like switch 110 or any of the switchesillustrated in FIG. 5B, is preferably implemented with a suitablesemiconductor switching device. During a second switching period,switches 110 and 112 reverse the positions shown in FIG. 5B so that therespective electrical charges in capacitors 111 and 113 are summed andapplied to the inverting input of an operational amplifier 114.Operational amplifier 114 is configured as an integrator with a feedbackcapacitor 115 having a capacitance value C₁ coupled between its outputand its inverting input. The output signal of operational amplifier 114is supplied to one pole of a SPDT sampling switch 116. The integratedoutput voltage of operational amplifier 115 is supplied by switch 116 toa capacitor 117 having a capacitance value _(g5) C.sub. 2 to chargecapacitor 117 to the integrated output voltage during the firstswitching period when the other side of capacitor 117 is connected by aSPDT switch 118 to ground. During the second switching period, switches116 and 118 reverse the positions shown in FIG. 5B so that theelectrical charge in capacitor 117 is applied to the inverting input ofan operational-amplifier 119. Operational amplifier 119 is alsoconfigured as an integrator with a feedback capacitor 126 having acapacitance value C₂ coupled between its output and its inverting input.The output signal of operational amplifier 119 is supplied from aninverter 120 to one pole of a double-pole, double throw (DPDT) switch121 which in the second switching period is connected to a capacitor 122having a capacitance value _(g2) C₁ to charge capacitor 122 to the inputvoltage level during the second switching period when the other side ofcapacitor 122 is connected by a SPDT switch 123 to ground. During thefirst switching period any electrical charge in capacitor 122 issupplied to the inverting terminal of operational amplifier 114 thuscompleting the feedback path internal to resonator 200' as shown in FIG.5A. The output signal of operational amplifier 119 is also supplied toA/D converter 14 and then to D/A converter 15 such that the output ofD/A converter 14 is supplied to the other pole of switch 121. During thefirst switching period, any charge in a capacitor 124 having acapacitance value of _(g3) C₁ is directly supplied to the invertingterminal of operational amplifier 114 thereby providing the scaledsignal supplied by the scaling unit of feedback generator 206, as shownin FIG. 5A. During the first switching period, the output signal of D/Aconverter 15 also charges capacitor 113 when the other side of capacitor113 is connected to ground. During the second switching period, theelectrical charge in capacitor 113 is supplied to the inverting terminalof operational amplifier 114 thereby providing the signal correspondingto the delayed signal by the delay unit in feedback generator 206, asshown in FIG. 5A. The following capacitance ratios make the SC circuitimplementation of FIG. 5B fully consistent with the embodiment of FIG.5A

    g1g5=k.sub.1 ;

    g2g5=2(1-Cosθ);

    g4g5=k.sub.1 ; and

    g3g5=2k.sub.1 Cosθ

and wherein k₁ =k_(1a) k_(lb).

Although FIG. 5B illustrates, by way of example and not of limitation, asingle-ended circuit, a fully differential implementation capable ofoperating in a mode suitable for handling differential signals isgenerally preferred in actual practice due to its improved power supplynoise immunity and rejection of even-order nonlinearities. An example ofsuch fully differential implementation is described by D. B. Ribner, etal in "A third-Order Multistage Sigma-Delta Modulator with ReducedSensitivity to Nonlinearities", IEEE, Journal of Solid State Circuits,Vol. 26, No. 12, Dec., 1991, pp. 1764-1773, which is herein incorporatedby reference. In a fully differential implementation, inverter 120 issimply implemented by reversal of the balanced signal path.

Another modulation stage 100" implementation using a resonatorconstructed with basic integrating units in accordance with anotheraspect of the invention is illustrated in FIG. 6A. Like resonator 200'of FIG. 5A, resonator 200" includes an analog subtracter 210 whichreceives a minuend input analog signal and a feedback subtrahend signalfor producing a difference output signal. An integrator 212 receives thedifference output signal to generate a first integrated output signal inresponse thereto. Unlike resonator 200' of FIG. 5A, resonator 200"includes a two-input adder 218 for receiving the first integrated outputsignal as an input signal to its first input and for receiving at itssecond input a compensation signal for producing a combined outputsignal which is produced in a compensation signal generator 220 inresponse to the output signal from D/A converter 15. Delayed integrator214 delays and integrates the combined output signal to generate asecond integrated output signal in response thereto. The secondintegrated output signal is the output signal of resonator 200". For theembodiment shown in FIG. 6A the scaling coefficients can be selectedsuch that h₁ =1/k_(la) k_(lb) ; a₁ =1-2Cosθ; a₂ =-2Cosθ and b₁=2(1-Cosθ) so as to provide suitable scaling regardless of the value ofthe arbitrary bandpass frequency at which the Δ--Σ modulator stage isoperated. It is noted that feedback generator 206 used in the embodimentof FIG. 6A comprises only a unit delay path whereas feedback generator206 used in the embodiment of FIG. 5A comprises a combined path made upof a unit delay path and a nondelayed path. In each case, the overallresponse is consistent with a resonator as depicted in FIG. 3 whichallows for implementation of delta-sigma (Δ--Σ) bandpass modulatorshaving an arbitrary bandpass frequency F_(bp).

A practical implementation for the modulation stage of FIG. 6A employsswitched capacitor (SC) integrators as shown in FIGS. 6B. In particular,the analog sampled-data input voltage (e.g., x(nT)) is supplied to onepole of a single-pole, double throw (SPDT) sampling switch 301. Thisswitch in practice is implemented with semiconductor switching devices,but for simplicity of illustration, is shown as a mechanical switch. Theanalog sampled-data input voltage x(nT) is supplied by switch 301 to acapacitor 302 having a capacitance value _(g1) C₁ to charge capacitor302 to the input voltage level during a first switching period when theother side of capacitor 302 is connected by SPDT switch 303 to ground.Also during the first switching period, switch 303 connects a capacitor305 having a capacitance value of _(g3) C₁ to ground. Switch 303, likeswitch 110 or any of the switches illustrated in FIG. 6B, is preferablyimplemented with a suitable semiconductor switching device. During asecond switching period, switches 301 and 303 reverse the positionsshown in FIG. 6B so that the respective electrical charges on capacitors302 and 305 are summed and applied to the inverting input of anoperational amplifier 304. Operational amplifier 304 is configured as anintegrator with a feedback capacitor 306 having a capacitance value C₁coupled between its output and its inverting input. The output signal ofoperational amplifier 304 is supplied to one pole of a SPDT samplingswitch 307. The integrated output voltage of operational amplifier 306is supplied by switch 307 to a capacitor 308 having a capacitance value_(g5) C₂ to charge capacitor 308 to the integrated output voltage levelduring the first switching period when the other side of capacitor 308is connected by a SPDT switch 309 to ground. Also during the firstswitching period, switch 309 connects a capacitor 312 having acapacitance value of _(g4) C₂ to ground. During a second switchingperiod, switches 307 and 309 reverse the positions shown in FIG. 6B sothat the respective electrical charges in capacitors 308 and 312 aresummed and applied to the inverting input of an operational amplifier310. Operational amplifier 310 is also configured as an integrator witha feedback capacitor 311 having a capacitance value C₂ coupled betweenits output and its inverting input. The output signal of operationalamplifier 310 is supplied through an inverter 320 to one pole of a SPDTswitch 313 which, in the second switching period, is connected to acapacitor 314 having a capacitance value _(g2) C₁ to charge capacitor314 to the input voltage level during the second switching period whenthe other side of capacitor 314 is connected by a SPDT switch 315 toground. During the first switching period any electrical charge incapacitor 314 is supplied to the inverting terminal of operationalamplifier 304, thus completing the feedback path internal to resonator200" as shown in FIG. 6A. The output signal of operational amplifier 310is also supplied to A/D converter 14 and then to D/A converter 15. Theanalog output signal of D/A converter 15 is supplied to one pole of aSPDT switch 316. During the second switching period, any charge oncapacitor 3 12 is supplied to the inverting terminal of operationalamplifier 310, thereby providing the compensation signal supplied bycompensation signal generator 220 shown in FIG. 6A. During the firstswitching period, the output signal of D/A converter 15 is also suppliedto charge capacitor 305 when the other side of capacitor 305 isconnected by switch 303 to ground. During the second switching period,the electrical charge on capacitor 305 is supplied to the invertingterminal of operational amplifier 304,thereby providing the sole delayedsignal supplied by the unit delay in feedback generator 206 shown inFIG. 6A. The following capacitance ratios make the SC circuitimplementation of FIG. 6B fully consistent with the embodiment of FIG.6A:

    g1g5=k.sub.1 ;

    g2g5=2(1-Cosθ);

    g3g5=k.sub.1 (1-2Cosθ); and

    g4=-2k.sub.1 Cos θ

and wherein k₁ =k_(la) k_(lb).

Although FIG. 6B illustrates a single-ended circuit, a fullydifferential implementation is preferably in practice, as suggested inthe discussion of FIG. 5B.

The new bandpass modulators of the invention, shown in FIGS. 7 and 8,are improvements over the prior art modulators of FIGS. 1 and 2,respectively. FIG. 7 shows a Multiple Second-Order Arbitrary FrequencyCascade modulator which is designated MSOAFC1 using an extension to theterminology introduced in the Ribner paper, supra, which is herebyincorporated by reference. The MSOAFC1 implementation uses quantizationsignals rather than resonator signals as input signals to successivestages, using the approach explained in the context of FIG. 1. Thevarious g, h, j and k scaling coefficients in this modulator have thesame values as the same respective coefficients in the modulator ofFIG. 1. This modulator differs from the modulator of FIG. 1 in that ithandles bandpass signals centered at an arbitrary frequency instead ofbandpass signals at a single bandpass frequency and is thereforesuitable for a wide array of applications. Comparing FIGS. 1 and 7, itwill be noted that the bandpass modulator of FIG. 1 which has a bandpasslimited to one fourth of the sampling frequency has been replaced with abandpass modulator having an arbitrary center frequency and which maytake the form of any of the embodiments shown in FIGS. 4 through 6. TheV₁ output signal of the first stage 10' is delayed by a delay element43' to compensate for the delay in the V_(N) output signal of the NthΔ--Σ modulator stage 30'. The V_(i) output signal of the ith Δ--Σmodulator stage 20' is likewise delayed, and is additionally digitallyfiltered by a notch filter 44' with z domain transfer function(1-2cosθ_(z) ⁻²)^(i-1). The V_(N) output signal of the Nth Δ--Σmodulator 30' is filtered by a notch filter with transfer function (1-2cosθ_(z) ⁻¹ +z⁻²)^(N-1) in filter element 45'.

The Multiple Second-Order Arbitrary Frequency Cascade modulatordesignated MSOAFC2, shown in FIG. 8, employs integrator signal cascadingusing the approach explained in the context of FIG. 2. The various g, jand k scaling coefficients in the MSOAFC2 modulator of FIG. 8 have thesame values as the same respective coefficients in the modulator of FIG.2. Contrasting FIGS. 2 and 8, delay/cosine filter elements 44 of FIG. 2have been replaced by delay/notch filter elements 44' and cosine filterelement 45 of FIG. 2 has been replaced by notch filter 45' having theaforementioned transfer function.

The output equation for each of the new bandpass modulators is

    Y(z)=z.sup.-2N x(z)+g.sub.N (1-2cosθ.sub.z.sup.-1 +z.sup.-2).sup.N Z.sub.N(Z).                                               (5)

The corresponding magnitude noise transfer functions for each of the newbandpass modulators is ##EQU10##

One of the motivations for using cascaded modulators is that stabilityis insured if each stage is of order two or lower. Therefore, theMSOAFC1 and MSOAFC2 modulators are unconditionally stable since they arecomprised of second-order stages. This is a significant advantage overprior art single-loop bandpass implementations in R. Schreier and M.Snelgrove, supra.

As to performance of the invention using conventional one micron CMOS(complementary metal-oxide-semiconductor) technology, it is expectedthat 16-bit A/D conversion of signals centered at 2.5 MHz with 150 kHzbandwidth is feasible, as is 12-bit conversion of signals centered at 10MHz with 1.25 MHz bandwidth. Conventional A/D conversion in one micronCMOS is capable of only 16-bit and 12-bit resolution up to 80 kHz and 1MHz signal frequencies, respectively.

While the invention has been described in terms of several preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

What is claimed is:
 1. An improved oversampling delta-sigmaanalog-to-digital converter system for high-frequency, narrow-bandsignals, said system having a plurality of delta-sigma modulator stageshaving an arbitrary band-pass frequency F_(bp) situated below at leastone half of a sampling frequency Fs for providing respective digitaloutput signals responsive to respective analog input signals, each ofsaid modulator stages including an analog-to-digital converter andhaving a digital-to-analog converter in a feedback loop, said improvedoversampling converter system comprising:a resonator in each respectivemodulator stage situated to provide analog signals to saidanalog-to-digital converter in said stage and having a z transformtransfer function ##EQU11## wherein θ is a phase angle defined asθ=2π(F_(bp) /F₂); and means for combining the digital output signals ofsaid plurality of delta-sigma modulator stages to suppress, in aresulting combined highly stable signal, quantization noise arising inat least one of said stages.
 2. The improved oversampling delta-sigmaanalog-to-digital converter system of claim 1, further comprising:meansfor applying an analog signal to be digitized by said improvedoversampling delta-sigma analog-to-digital converter system as theanalog input signal of a first one of said plurality of delta-sigmamodulator stages; and quantization noise-producing means in each of saidplurality of delta-sigma modulator stages except a final stage fordetermining the quantization noise of said delta-sigma modulator stagesexcept the final stage, respectively, each said quantizationnoise-producing means being coupled to a subsequent one of saiddelta-sigma modulator stages, respectively, to provide an analog inputsignal thereto; said digital-to-analog converter in each respective oneof said plurality of delta-sigma modulator stages being coupled toreceive output signals from said analog-to-digital converter.
 3. Theimproved oversampling delta-sigma analog-to-digital converter system ofclaim 2 wherein said means for combining the digital output signals ofsaid plurality of delta-sigma modulator stages comprises:notch filtermeans having a z domain transfer function

    (1-2Cosθ.sub.z.sup.-1 +z.sup.-2).sup.N-1

for digitally filtering output signals of said means delta-sigmamodulator stage, N being the total number of said delta-sigma modulatorstages; delay means for providing a compensating delay to the outputsignals of the first delta-sigma modulator stage; and means forcombining output signals from said notch filter means and said delaymeans to produce an output signal for said oversampling delta-sigmaanalog-to-digital converter system.
 4. The improved oversamplingdelta-sigma analog-to-digital converter system of claim 3 wherein saidmeans for combining the digital output signals of said plurality ofdelta-sigma modulator stages further comprises additional notch filtermeans having a z domain transfer function

    (1-2Cosθ.sub.z.sup.-1 +z.sup.-2).sup.N-2

for digitally filtering output signals from the next-to-finaldelta-sigma modulator stage; and wherein said means for combining outputsignals from said notch filter means and said delay means also combinesoutput signals of said additional notch filter means.
 5. The improvedoversampling delta-sigma analog-to-digital converter system of claim 1wherein each respective one of said plurality of delta-sigma modulatorstages comprises:a two-input adder having its output coupled to saidresonator therein; an input delay unit for receiving the analog inputsignal therein and delaying said analog signal to generate a delayedanalog input signal, said delayed analog input signal supplied as aninput signal to a first input of said two-input adder therein, the inputdelay unit of a first delta-sigma modulator stage coupled to receive ananalog signal which constitutes the analog signal therein to bedigitized by said improved oversampling delta-sigma analog-to-digitalconverter system; and feedback generating means coupled to receive theoutput signal from said digital-to-analog converter therein and forgenerating a feedback signal for application to a second input of saidtwo-input adder therein.
 6. The improved oversampling delta-sigmaanalog-to-digital converter system of claim 5 further including;meansfor coupling the output of the resonator of said first stage to an inputdelay unit of a second delta-sigma modulator stage; and means forcoupling the output of the resonator of said second stage to an inputdelay unit of a third delta-sigma modulator stage.
 7. The improvedoversampling delta-sigma analog-to-digital converter system of claim 6wherein said means for combining the digital output signals of saidplurality of delta-sigma modulator stages comprises:notch filter meanshaving a z domain transfer function

    (1-2Cosθ.sub.z.sup.-1 +z.sup.-2).sup.2

for digitally filtering the output signal of said third delta-sigmamodulator stage; delay means for providing a compensating delay to theoutput signal of the first delta-sigma modulator stage; and means forcombining output signals of said notch filter means and said delay meansto produce an output signal for said oversampling delta-sigmaanalog-to-digital converter system.
 8. The improved oversamplingdelta-sigma analog-to-digital converter system of claim 7 wherein saidmeans for combining the digital output signals of said plurality ofdelta-sigma modulator stages further comprises additional notch filtermeans having a z domain transfer function

    1-2Cosθ.sub.z.sup.-1 +z.sup.-2

for digitally filtering the output signal of the second delta-sigmamodulator stage; and wherein said means for combining output signals ofsaid notch filter means and said delay means also combines the outputsignal of said additional notch filter means.
 9. The improvedoversampling delta-sigma analog-to-digital converter system of claim 5wherein said feedback generating means comprises a unit delay path. 10.The improved oversampling delta-sigma analog-to-digital converter systemof claim 5 wherein said feedback generating means comprises a combinedpath having a unit delay path and a nondelayed path.
 11. The improvedoversampling delta-sigma analog-to-digital converter system of claim 1wherein at least one of said resonators comprises:an analog subtracterfor receiving a minuend input analog signal and a feedback subtrahendsignal and for producing a difference output signal; an integrator forreceiving said difference output signal and for generating a firstintegrated output signal in response thereto; a delayed integrator fordelaying and integrating said first integrated output signal to generatea second integrated output signal in response thereto, said secondintegrated output signal being the output signal of said one of saidresonators; and means for generating said feedback subtrahend signalfrom said second integrated output signal.
 12. The improved oversamplingdelta-sigma analog-to-digital converter system of claim 11 wherein saidintegrator receiving said difference output signal and said delayedintegrator comprise respective switched capacitor integrators.
 13. Theimproved oversampling delta-sigma analog-to-digital converter system ofclaim 1 wherein at least one of said resonators comprises:an analogsubtracter for receiving a minuend input analog signal and a feedbacksubtrahend signal for producing a difference output signal; anintegrator for receiving said difference output signal and forgenerating a first integrated output signal in response thereto; atwo-input adder for receiving said first integrated output signal at afirst input and for receiving a compensation signal at a second input,for producing a combined output signal; a delayed integrator fordelaying and integrating said combined output signal and for generatinga second integrated output signal in response thereto, said secondintegrated output signal being the output signal of said one of saidresonators; means for generating said feedback subtrahend signal fromsaid second integrated output signal; and means for generating saidcompensation signal from the output signal of the digital-to-analogconverter therein.
 14. The improved oversampling delta-sigmaanalog-to-digital converter system of claim 13 wherein said integratorand delayed integrator comprise respective switched capacitorintegrators.